1. Field of the Invention
The present invention relates to an image processing device in which a DRAM is used as a frame buffer.
2. Description of the Related Art
FIG. 1 shows a block diagram of an image processing device in the related art. As shown in the figure, the image processing device 91 is connected to a frame buffer 93 which is formed of a DRAM (Dynamic RAM). The image processing device 91 includes an internal pixel calculating circuit 95, a pixel buffer 97 and a DRAM interface 99. The internal pixel calculating circuit 95 calculates pixel information from input data. The pixel buffer 97 cancels a difference in operation speeds between the frame buffer 93 and the internal pixel calculating circuit 95. The DRAM interface transmits data to and receives data from the frame buffer 93.
In the image processing device 91, the internal pixel calculating circuit 95 calculates the pixel information including coordinate positions, color information and so forth. The pixel information is supplied to the frame buffer 93 via the pixel buffer 97 and DRAM interface 99, and the frame buffer 93 stores the pixel information.
Recently, between the image processing device 91 and the frame buffer 93, a 64-bit-width data bus 101 is connected. Thereby, the number of pixels which can be accessed at one time increases. For example, as shown in FIG. 2, when the information of one dot is represented by 16 bits, 4 dots can be accessed in one time access. In the frame buffer 93 formed of the DRAM, by increasing the number of bit read/write operations which can be performed at one time in one page mode operation, it is possible to increase the number of dots which can be accessed at one time. Thus, image drawing performance can be improved. The page mode is an access mode in which, as shown in FIG. 3, a RAS (Row Address Strobe ` `, representing active-low or low-enable) signal is active while an address is changed, and, in response thereto, a CAS (Column Address Strobe) signal is repetitively active, and thus, data reading and writing can be efficiently performed. At this time, all of the row addresses of data which are successively accessed are equal to each other. Hereinafter, the number of the operations of causing thn CAS signal to be successively active in one page mode operation will be referred to as `the number of times of CAS in the page mode`.
In the image processing device 91 in the related art, the number of times of CAS in the page mode is fixed. For example, the number of times of CAS in the page mode at one time is fixed to be four. Assuming that 4 dots can be processed in one access, in a case of drawing a polygon 103 as shown in FIG. 4, when the line a-b is drawn, although only two dots of data should be written, in one page mode operation, 16 dots (4 (dots).times.4 (times)) of data is accessed. Accordingly, access to 14 dots is useless. In the image processing device 91 in the related art, because the number of access operations in one page mode operation is fixed, efficiency may be degraded in consideration of the number of dots which should be processed on a particular occasion.